![Gate-Level Design Optimization](https://d27wgn5g4t3wja.cloudfront.net/img/f24c45a7-1422-08df-aa3c-b00280617b97/331912.png)
Gate-Level Design Optimization
DeFacTo Technologies (DeFacTo)
After logic synthesis, STAR helps reaching power, performance and area (PPA) requirements for complex SoCs is becoming a real challenge. Large design netlists are restructured and optimized to reach aggressive PPA requirements, cost-effectively.