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RISC-V
open specification for an Instruction Set Architecture (ISA) based on reduced instruction set computer (RISC) principles.
See Also: ARM
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Free Imperas RISC-V Instruction Set Simulator
riscvOVPsim
*RiscvOVPsim - RISC-V Instruction Set Simulator (ISS) - fast, simple, easy to use, cross software development for embedded systems*The riscvOVPsim ISS is an ideal starting point for an embedded software development project. *RiscvOVPsim allows the development and debug of code for the target RISC-V processor on an x86 host PC with the minimum of setup and effort. It simply requires the cross compilation of your application and running riscvOVPsim with an argument to specify the name of the application object.
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RISC-V Processor IP Core Evaluation Kit
The EMSA5 demo platform is an ideal tool for evaluating the RISC-V processor IP core EMSA5. It contains an Artix®-7 35T FPGA Arty evaluation board with implemented EMSA5-IP core. Thanks to the included peripherals and expansion interfaces, the kit is ideal for numerous applications. The kit is JTAG programmable and includes Quad SPI Flash, a JTAG port, 10/100 Mb/s Ethernet and a USB-UART bridge, four Pmod connectors and an Arduino Shield expansion connector.
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Computing
CAES offers multi-architectural computing platforms tailored to fit your mission requirements. We offer highly integrated, full featured SPARC®-based and RISC-V®-based microprocessor and microcontroller solutions as well as Arm®-based microcontrollers.
